As data transfer rates continue to increase, it becomes increasingly difficult to build robust signaling systems that are relatively error free and low power. In digital memory systems in particular, sophisticated, relatively power-hungry circuitry is often employed in memory devices to achieve exact timing alignment with a clock signal provided by a memory controller. In addition to conventional use of relatively power-hungry circuitry in memory devices (such as a phase-locked loop, for example) to drive an on-memory-chip clock distribution network, conventional design wisdom typically calls for overdesign of logic gates, under the assumption that manufacturing tolerances will produce a predictable range of performance capabilities at a given clock rate and power supply and under the assumption that such overdesign is necessary to ensure that almost every manufactured device will meet specification. While such overdesign is generally quite successful at minimizing the number of products not meeting specification, it typically results in excessive power consumption for the great majority of devices which were manufactured at faster process corners while operating at a performance level set by the slowest process corner.
What is needed is a scheme to achieve relatively precise control over memory timing. A need also exists for a memory system that economizes power; further still, a need exists for a memory clocking scheme that better tolerates design process variations, enabling relatively simpler memory device design as well as minimization of power used by devices manufactured in the faster process corners. The present invention satisfies these needs and provides further, related advantages.